1. Technical Field
The disclosure relates to a stacked structure, and more particular, to a semiconductor device stacked structure.
2. Related Art
In the current information society, the trend of electronic product design is toward lightweight, thin, short, and small in size. As such, the development of various packaging technologies, such as the stack-type semiconductor device packaging technology, is advantageous in miniaturization of the semiconductor package.
In a stack-type semiconductor device package, a plurality of semiconductor devices is packaged in the same package structure in a vertically stacked manner. This can increase package density to miniaturize the package structure, reduce the length of signal transmission path between the semiconductor devices by means of a 3D-stacked manner to increase the speed of signal transmission between the semiconductor devices, as well as combine semiconductor devices having different functions into the same package structure.
In the existing stack-type semiconductor device package, a plurality of through silicon vias (TSV) is usually formed in the semiconductor devices to provide electrical connection paths in a vertical direction. The TSV requires good thermo-mechanical reliability for mass production. However, due to the difference of the coefficient of thermal expansion (CTE) between the TSV filler material and the silicon chip, thermal stress tends to be produced in the TSV, resulting in a plastic deformation, stress induced voiding and stress migration. The interfacial stress can cause peeling and TSV pop-up or even lead to an irremediable failure such as chip fracture.